This invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, in particular, a technique effective when adapted for the so-called damascene method wherein an interconnection having copper as a main conductive layer is formed by cutting a groove in an insulating film, forming a copper film to be embedded in the groove and polishing by CMP (Chemical Mechanical Polishing).
Attendant on the recent tendency to miniaturizing an interconnection in a semiconductor integrated circuit device, a deterioration in the performance of the semiconductor integrated circuit device resulting from an increase in interconnection resistance or interconnection delay has come to be a problem. It has led to a serious problem particularly in a high-performance logic LSI as a factor for disturbing its performance. As described on pages 15 to 21 in the Preprint of 1993 VMIC (VLSI Multilevel Interconnection Conference), a method for forming an interconnection pattern in an interconnection groove by embedding a metal, which has copper (Cu) as a main conductive layer, in an interconnection groove formed in an insulating film and then removing the unnecessary portion of the metal outside the interconnection groove by chemical mechanical polishing (CMP) is now under investigation.
Described in Japanese Patent Application Laid-Open No. Hei 9-306915 is a technique which comprises forming an interconnection groove in a silicon oxide film on a semiconductor substrate, depositing a titanium nitride film and copper film by sputtering, filling the groove with copper by reflow, removing the copper film outside the groove by CMP and then heat treating in a hydrogen atmosphere. According to it, defects in the copper interconnection can be reduced by this technique.
Described in Japanese Patent Application Laid-Open No. Hei 10-56014 is a technique comprising polishing a material, which has a titanium nitride film and tungsten film and is formed over a semiconductor substrate, by CMP and subjecting the polished surface to plasma treatment with a halogen-based mixed gas. According to it, no interconnection short-circuit occurs even if micro scratches are formed by CMP.
Described in Japanese Patent Application Laid-Open No. Hei 10-56014 is a technique comprising forming a photosensitive SOG film over a base on which an interconnection is to be formed, forming an interconnection groove in the SOG film, forming a titanium nitride film, a copper film and a copper titanium alloy film, leaving the films only inside of the interconnection groove by CMP, and heat treating in an ammonia atmosphere to form a titanium nitride film over the surface layer of the copper titanium alloy film.
Described in Japanese Patent Application Laid-Open No. Hei 11-16912 is a technique of subjecting the surface of a through-hole or the like of a copper interconnection formed by the damascene method to plasma treatment in an atmosphere such as ammonia.